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integrated fast ethernet controller for pci express? applications datasheet rev. 1.2 05 may 2006 track id: jatr-1076-21 realtek semiconductor corp. no. 2, innovation road ii, hsinchu science park, hsinchu 300, taiwan tel.: +886-3-578-0211. fax: +886-3-557-6047 www.realtek.com.tw RTL8101E-GR www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express ii track id: jatr-1076-21 rev. 1.2 copyright ?2007 realtek semiconductor corp. all rights reserve d. no part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of realtek semiconductor corp. disclaimer realtek provides this document ?as is?, without wa rranty of any kind, neither expressed nor implied, including, but not limited t o, the particular purpose. realtek may make improvements and/or changes in this document or in the product described in this document at any time. this document could include technical inaccuracies or typographical errors. trademarks realtek is a trademark of realtek semiconductor cor poration. other names mentioned in this document are trademarks/registered trademarks of their respective owners. using this document this document is intended for the software engin eer?s reference and provides detailed programming information. though every effort has been made to ensure that th is document is current and accurate, more information may have become available subsequent to the producti on of this guide. in that event, please contact your realtek representative for additional information that may help in the development process. revision history revision release date summary 1.0 2005/11/11 first release. 1.1 2006/04/07 changed figure 1, pin assignments, page 3. changed table 6, reference, page 5. changed table 8, power & ground, page 6. 1.2 2007/05/05 changed esr data (table 13, page 15). added table 14, page 16. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express iii track id: jatr-1076-21 rev. 1.2 table of contents 1. general desc ription .................................................................................................... 1 2. features ....................................................................................................................... .2 3. system app lications .................................................................................................... 2 4. pin assign ments........................................................................................................... 3 4.1. p ackage i dentification ...............................................................................................................3 5. pin descri ptions........................................................................................................... 4 5.1. p ower m anagement /i solation ...................................................................................................4 5.2. pci e xpress i nterface .................................................................................................................4 5.3. eeprom.................................................................................................................... .....................4 5.4. t ransceiver i nterface ................................................................................................................5 5.5. c lock ............................................................................................................................... ...............5 5.6. r eference ............................................................................................................................... .......5 5.7. led s ............................................................................................................................... ................5 5.8. p ower & g round ...........................................................................................................................6 5.9. nc (n ot c onnected ) p ins ............................................................................................................6 6. functional de scription................................................................................................ 7 6.1. pci e xpress b us i nterface ..........................................................................................................7 6.1.1. pci express transmitter........................................................................................................ .................................7 6.1.2. pci expres s receiver ........................................................................................................... ..................................7 6.2. led f unctions ..............................................................................................................................7 6.2.1. link monitor................................................................................................................... ........................................7 6.2.2. rx led ......................................................................................................................... ..........................................8 6.2.3. tx led ......................................................................................................................... ..........................................8 6.2.4. tx/rx led ...................................................................................................................... ........................................9 6.2.5. link/act led ................................................................................................................... ...................................9 6.3. phy t ransceiver ........................................................................................................................10 6.3.1. phy tran smitter ................................................................................................................ ...................................10 6.3.2. phy r eceiver................................................................................................................... .....................................10 6.4. eeprom i nterface ....................................................................................................................11 6.5. p ower m anagement ...................................................................................................................12 6.6. v ital p roduct d ata (vpd) .......................................................................................................14 7. characteri stics ........................................................................................................... 15 7.1. a bsolute m aximum r atings .....................................................................................................15 7.2. r ecommended o perating c onditions ......................................................................................15 7.3. c rystal r equirements ..............................................................................................................15 7.4. t ransformer c haracteristics .................................................................................................16 7.5. t hermal c haracteristics .........................................................................................................16 7.6. dc c haracteristics ...................................................................................................................16 7.7. ac c haracteristics ...................................................................................................................17 www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express iv track id: jatr-1076-21 rev. 1.2 7.7.1. serial eeprom in terface timing ................................................................................................. .......................17 7.8. pci e xpress b us p arameters ....................................................................................................18 7.8.1. differential transm itter para meters............................................................................................ .........................18 7.8.2. differential recei ver parameters ............................................................................................... ..........................19 7.8.3. refclk para meters.............................................................................................................. ..............................19 7.8.4. auxiliary signal ti ming parameters ............................................................................................. .......................21 8. mechanical di mensions ............................................................................................ 22 9. ordering info rmation ............................................................................................... 22 list of tables table 1. power management/isolation .......................................................................................... ...........4 table 2. pci express interface ............................................................................................... ..................4 table 3. eeprom .............................................................................................................. ......................4 table 4. transceiver interface ............................................................................................... ...................5 table 5. clock............................................................................................................... ............................5 table 6. reference ........................................................................................................... .........................5 table 7. leds ................................................................................................................ ...........................5 table 8. power & ground...................................................................................................... ...................6 table 9. nc (not connected) pins ............................................................................................. ..............6 table 10. eeprom interface.................................................................................................... ...............11 table 11. absolute maximum ratings............................................................................................ .........15 table 12. recommended operating conditions.................................................................................... ...15 table 13. crystal requirements ................................................................................................ ...............15 table 14. transformer characteristics ......................................................................................... ............16 table 15. thermal characteristics............................................................................................. ...............16 table 16. dc characteristics.................................................................................................. ..................16 table 17. eeprom access timing parameters ..................................................................................... .17 table 18. differential transmitter pa rameters ................................................................................. ........18 table 19. differential receiver parameters.................................................................................... ..........19 table 20. refclk parameters ................................................................................................... .............19 table 21. auxiliary signal timing parameters .................................................................................. ......21 table 22. ordering information................................................................................................ ................22 www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express v track id: jatr-1076-21 rev. 1.2 list of figures figure 1. pin assignments .................................................................................................... ....................3 figure 2. rx led ............................................................................................................. ........................8 figure 3. tx led............................................................................................................. .........................8 figure 4. tx/rx led.......................................................................................................... ......................9 figure 5. link/act led ....................................................................................................... ................9 figure 6. serial eeprom interface timing ..................................................................................... .....17 figure 7. refclk single-ended measurement points for t rise and t fall ..............................................20 figure 8. refclk single-ended measurement points for v ovs , v uds, and v rb ......................................20 figure 9. refclk differential measurement points for t period , duty cycle, and jitter .......................20 figure 10. refclk v cross range .............................................................................................................21 figure 11. auxiliary signal timing............................................................................................ ..............21 www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express 1 track id: jatr-1076-21 rev. 1.2 1. general description the realtek rtl8101e fast ethernet controller combines an ieee 802.3 10/100base-t compliant media access controller (mac), pci expr ess bus controller, and embedded me mory. with state-of-the-art dsp technology and mixed-mode signal technology, the rtl8101e offers high-speed transmission over cat 5 utp cable or cat 3 utp ( 10mbps only) cable. functions such as crossover detection & auto-correction, polarity correction, adaptive e qualization, cross-talk can cellation, echo cancellation, timing recovery, and error correction are implemented to provide robust transmission and reception capability at high speeds. the device supports the pci expres s 1.0a bus interface for host communications with power management and is compliant with the ieee 802.3u specification for 10/100mbps ethernet. it also supports an auxiliary power auto-detect function, and will auto-c onfigure related bits of the pci power management registers in pci configuration space. advanced configuration power management in terface (acpi)?power mana gement for modern operating systems that are capable of operati ng system-directed power management (ospm)?is supported to achieve the most efficient power mana gement possible. pci message signaled interrupt (msi) is also supported. in addition to the acpi feature, remo te wake-up (including amd magic packet ? , re-linkok, and microsoft ? wake-up frame) is supported in both ac pi and apm (advanced power management) environments. to support wol from a deep power dow n state (e.g., d3cold, i.e. main power is off and only auxiliary exists), the auxiliar y power source must be able to provide the needed power for the rtl8101e. the rtl8101e is fully compliant with microsoft ? ndis5 (ip, tcp, udp) checksum and segmentation task-offload features, and suppor ts ieee 802 ip layer 2 priority encoding and ieee 802.1q virtual bridged local area network (vlan). the above f eatures contribute to lowering cpu utilization, especially benefiting performance when in operation on a network server. the device also features next-g eneration interconnect pci expres s technology. pci express is a high-bandwidth, low-pin-count, serial interconnect technology that offe rs significant improvements in performance over conventional pci and also maintains software co mpatibility with existing pci infrastructure. the rtl8101e is suitable for multiple market segm ents and emerging applications, such as desktop, mobile, workstation, server, communications platforms, and embedded applications. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express 2 track id: jatr-1076-21 rev. 1.2 2. features ? integrated 10/100 transceiver ? auto-negotiation with next page capability ? supports pci express? 1.0a ? supports pair swap/polarity/skew correction ? crossover detection & auto-correction ? wake-on-lan and remote wake-up support ? microsoft ? ndis5 checksum offload (ip, tcp, udp) and largesend offload support ? supports full duplex flow control (ieee 802.3x) ? fully compliant with ieee 802.3, ieee 802.3u, ieee 802.3ab ? supports ieee 802.1p layer 2 priority encoding ? supports ieee 802.1q vlan tagging ? serial eeprom ? transmit/receive on-chip buffer support ? supports power down/link down power saving ? supports pci message signaled interrupt (msi) ? 64-pin qfn package 3. system applications ? fast ethernet on motherboard, notebook, or embedded system www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express 3 track id: jatr-1076-21 rev. 1.2 4. pin assignments figure 1. pin assignments 4.1. package identification ?green? package is indicated by a ?g? in the location marked ?t? in figure 1. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express 4 track id: jatr-1076-21 rev. 1.2 5. pin descriptions the signal type codes below are used in the following tables: i: input s/t/s: sustained tri-state o: output o/d: open drain t/s: tri-state bi-direc tional input/output pin 5.1. power management/isolation table 1. power management/isolation symbol type pin no description lanwakeb o/d 19 power management event: open drain, active low. used to reactivate the pci express slot?s main power rails and reference clocks. isolateb i 36 isolate pin: active low. used to isolate the rtl8101e from the pci express bus. the rtl8101e will not drive its pci express outputs (excluding lanwakeb) and will not sample its pci express input as long as the isolate pin is asserted. 5.2. pci express interface table 2. pci express interface symbol type pin no description refclk_p i 26 refclk_n i 27 pci express differential reference clock source: 100mhz 300ppm. hsop o 29 hson o 30 pci express transmit differential pair. hsip i 23 hsin i 24 pci express receive differential pair. perstb i 20 pci express reset signal: active low. when the perstb is asserted at power- on state, the rtl8101e returns to a pre-defined reset state and is ready fo r initialization and configuration after the de-assertion of the perstb. 5.3. eeprom table 3. eeprom symbol type pin no description eesk o 48 serial data clock. eedi/aux o/i 47 eedi: output to serial data input pin of eeprom. aux: input pin to detect if aux. powe r exists or not on initial power-on. this pin should be connected to eeprom. to support wakeup from acpi d3cold or apm power-down, this pin must be pulled high to aux. power via a resistor. if this pin is not pulled high to aux. power, the rtl8101e assumes that no aux. power exists. eedo i 45 input from serial data output pin of eeprom. eecs o 44 eecs: eeprom chip select. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express 5 track id: jatr-1076-21 rev. 1.2 5.4. transceiver interface table 4. transceiver interface symbol type pin no description mdip0 i/o 3 mdin0 i/o 4 in mdi mode, this pair acts as the bi_da+/- pair, and is the transmit pair in 10base-t and 100base-tx. in mdi crossover mode, this pair acts as the bi_db+/- pair, and is the receive pair in 10base-t and 100base-tx. mdip1 i/o 6 mdin1 i/o 7 in mdi mode, this pair acts as the bi_db+/- pair, and is the receive pair in 10base-t and 100base-tx. in mdi crossover mode, this pair acts as the bi_da+/- pair, and is the transmit pair in 10base-t and 100base-tx. 5.5. clock table 5. clock symbol type pin no description cktal1 i 60 input of 25mhz clock reference. cktal2 o 61 output of 25mhz clock reference. 5.6. reference table 6. reference symbol type pin no description rset i 64 reference. external resistor reference. 5.7. leds table 7. leds symbol type pin no description led0 o 57 led1 o 56 led2 o 55 led3 o 54 leds1-0 00 01 10 11 led0 tx/rx link10/ac t tx link10/act led1 link100 link100/act link link100/act led2 link10 full rx full led3 na na full na note 1: during power down mode, the led signals are logic high. note 2: leds1-0?s initial value comes from the 93c46. if there is no 93c46, the default value of the (leds1, leds0) = (1, 1). www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express 6 track id: jatr-1076-21 rev. 1.2 5.8. power & ground table 8. power & ground symbol type pin no description vdd33 power 16, 37, 46, 53 digital 3.3v power supply. vdd15 power 15, 21, 43, 49, 58 digital 1.5v power supply. avdd18 power 5, 8 analog 1.8v power supply. evdd18 power 22, 28 analog 1.8v power supply. avdd33 power 2 analog 3.3v power supply. egnd power 25, 31 analog ground. gnd power 65 ground.(exposed pad) vctrl15 o 63 1.5 voltage output supplies power to vdd15 power pin. vctrl18 o 1 1.8 voltage output supplies power to avdd18 and evdd18 power pin. note: refer to the most updated schematic circuit for correct configuration. 5.9. nc (not connected) pins table 9. nc (not connected) pins symbol type pin no description nc 9, 10, 11, 12, 13, 14, 17, 18, 32, 33, 34, 35, 38, 39, 40, 41, 42, 50, 51, 52, 59, 62 not connected. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express 7 track id: jatr-1076-21 rev. 1.2 6. functional description 6.1. pci express bus interface the rtl8101e complies with pci express base specification revision 1.0a, and runs at a 2.5ghz signaling rate with x1 link width, i.e., one transmit and one receiv e differential pair. the rtl8101e supports four types of pci express messages: inte rrupt messages, error messages, power management messages, and hot-plug messages. to ease pcb layout c onstraints, pci express la ne polarity reversal and link reversal are also supported. 6.1.1. pci express transmitter the rtl8101e?s pci express block receives digital da ta from the ethernet interface and performs data scrambling with linear feedback shift register (l fsr) and 8b/10b coding tec hnology into 10-bit code groups. data scrambling is used to reduce the possibili ty of electrical resona nce on the link, and 8b/10b coding technology is used to benefit embedded clocki ng, error detection, and dc balance by adding an overhead to the system through the addition of 2 extr a bits. the data code gr oups are passed through its serializer for packet framing. the generated 2.5gbps serial data is transmitted onto the pcb trace to its upstream device via a differential driver. 6.1.2. pci express receiver the rtl8101e?s pci express block receives 2.5gbps se rial data from its upst ream device to generate parallel data. the receiver?s pll circuits are re-synchronized to main tain bit and symbol lock. through 8b/10b decoding technology and data descrambling, the original digital data is recovered and passed to the rtl8101e?s internal ethernet mac to be transmitted onto the ethernet media. 6.2. led functions the rtl8101e supports four led signa ls in four different configurab le operation modes. the following sections describe the various led actions. 6.2.1. link monitor the link monitor senses link integrity, such as link10, link100, link10/100, link10/act, or link100/act. whenever link status is established, the specific link led pin is driven low. once a cable is disconnected, the link led pin is driven hi gh, indicating that no netw ork connection exists. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express 8 track id: jatr-1076-21 rev. 1.2 6.2.2. rx led in 10/100mbps mode, blinking of the rx led i ndicates that receive activity is occurring. power on receiving packet? led = high led = high for 40 ms led = low for 40 ms no yes figure 2. rx led 6.2.3. tx led in 10/100mbps mode, blinking of the tx led i ndicates that transmit activity is occurring. power on transmitting packet? led = high led = high for 40 ms led = low for 40 ms no yes figure 3. tx led www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express 9 track id: jatr-1076-21 rev. 1.2 6.2.4. tx/rx led in 10/100mbps mode, blinking of the tx/rx led indicat es that both transmit and receive activity is occurring. power on tx/rx packet? led = high led = high for 40 ms led = low for 40 ms no yes figure 4. tx/rx led 6.2.5. link/act led in 10/100mbps mode, blinking of the link/act led indicates th at the rtl8101e is linked and operating properly. when this led is high for extended periods, it indicates that a link problem exists. power on link? led = high led = low led = low for 40 ms no yes tx/rx packet? yes no led = high for 40 ms figure 5. link/act led www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express 10 track id: jatr-1076-21 rev. 1.2 6.3. phy transceiver 6.3.1. phy transmitter based on state-of-the-art dsp t echnology and mixed-mode signal processing technology, the rtl8101e operates at 10/100mbps over standa rd cat.5 utp cable (100mbps), and cat.3 utp cable (10mbps). mii (100mbps) mode the transmitted 4-bit nibbles (txd[3:0]) from the ma c, clocked at 25mhz (txc), are converted into 5b symbol code through 4b/5b coding technology, then through scrambling and serializing, are converted to 125mhz nrz and nrzi signals. after that, the nrzi signals are passed to the mlt3 encoder, then to the d/a converter and transmitted onto the media. mii (10mbps) mode the transmitted 4-bit nibbles (txd[3:0]) from the mac, clocked at 2.5mhz (txc), are serialized into 10mbps serial data. the 10mbps serial data is convert ed into a manchester-encoded data stream and is transmitted onto the media by the d/a converter. 6.3.2. phy receiver mii (100mbps) mode the mlt3 signal is processed with an adc, equalizer, blw (baseline wander) correction, timing recovery, mlt3 and nrzi decoder, descrambler, 4b /5b decoder, and is then presented to the mii interface in 4-bit-wide nibbles at a clock speed of 25mhz. mii (10mbps) mode the received differential signal is converted into a manchester-encoded st ream first. next, the stream is processed with a manchester decoder and is de-seria lized into 4-bit-wide nibbles. the 4-bit nibbles are presented to the mii interface at a clock speed of 2.5mhz. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express 11 track id: jatr-1076-21 rev. 1.2 6.4. eeprom interface the rtl8101e requires the attachment of an ex ternal eeprom. the 93c46/93c56 is a 1k-bit/2k-bit eeprom. the eeprom interface permits the rtl8101e to read from, and write data to, an external serial eeprom device. values in the external eeprom allow default fields in pci configuration space and i/o space to be overridden following a power-on or software eeprom auto-load command. the rtl8101e will auto-load values from the eeprom. if the eeprom is not present, the rtl 8101e initialization uses default values for the appropriate co nfiguration and operationa l registers. software can read and write to the eeprom using bit-bang accesses via the 9346cr re gister, or using pci vpd (vital product data). the interface consists of ees k, eecs, eedo, and eedi. the correct eeprom (i.e. 93c46/93c56) must be us ed in order to ensure proper lan function. table 10. eeprom interface eeprom description eecs 93c46/93c56 chip select. eesk eeprom serial data clock. eedi/aux input data bus/input pin to detect whether aux. power exists on initial power-on. this pin should be connected to eeprom. to support wakeup from acpi d3cold or apm power-down, this pin must be pulled high to aux. power via a resistor. if this pin is not pulled high to aux. power, the rtl8101e assumes that no aux. power exists. eedo output data bus. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express 12 track id: jatr-1076-21 rev. 1.2 6.5. power management the rtl8101e complies with acpi (rev 1.0, 1.0b, 2.0), pci power management (rev 1.1), pci express active state power management (aspm) , and network device class power management reference specification (v1.0a), such as to support an operating system-directed power management (ospm) environment. the rtl8101e can monitor the network for a wake up frame, a magic packet, or a re-linkok, and notify the system via a pci express power management event (pme) message, beacon, or lanwakeb pin when such a packet or event occurs. th en the system can be restored to a normal state to process incoming jobs. when the rtl8101e is in power down mode (d1 ~ d3): ? the rx state machine is stopped. the rtl8101e mon itors the network for wakeup events such as a magic packet, wakeup frame, and/or re-linkok, in order to wake up the system. when in power down mode, the rtl8101e will not reflect the status of any incoming packets in the isr register and will not receive any packets into the rx on-chip buffer. ? the on-chip buffer status and packets that have already been received into the rx on-chip buffer before entering power down m ode are held by the rtl8101e. ? transmission is stopped. pci express transactio ns are stopped. the tx on-chip buffer is held. ? after being restored to d0 state, the rtl8101e transmits data that was not moved into the tx on-chip buffer during power down mode. packets that we re not transmitted completely last time are re-transmitted. the d3cold_support_pme bit (bit15, pmc register) a nd the aux_i_b2:0 bits (bit8 :6, pmc register) in pci configuration space depend on the exis tence of aux power (bit15, pmc) = 1. if eeprom d3cold_support_pme bit (bit15, pmc) = 0, the above 4 bi ts are all 0?s. example: if eeprom d3c_support_pme = 1: ? if aux. power exists, then pmc in pci c onfig space is the same as eeprom pmc (if eeprom pmc = c2 f7, then pci pmc = c2 f7) ? if aux. power is absent, then pmc in pci conf ig space is the same as eeprom pmc except the above 4 bits are all 0?s (if eeprom pmc = c2 f7, then pci pmc = 02 76) in the above case, if wakeup support is desired when main power is off, it is suggested that the eeprom pmc be set to c2 f7 (realtek eeprom default value). if eeprom d3c_support_pme = 0: ? if aux. power exists, then pmc in pci c onfig space is the same as eeprom pmc (if eeprom pmc = c2 77, then pci pmc = c2 77) ? if aux. power is absent, then pmc in pci conf ig space is the same as eeprom pmc except the above 4 bits are all 0?s (if eeprom pmc = c2 77, then pci pmc = 02 76) in the above case, if wakeup support is not desired wh en main power is off, it is suggested that the eeprom pmc be set to 02 76. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express 13 track id: jatr-1076-21 rev. 1.2 link wakeup occurs only when the following conditions are met: ? the linkup bit (config3#4) is set to 1, the pmen bit (config1#0) is set to 1, and the corresponding wake-up method (message, beacon, or lanwakeb) can be asserted in the current power state. magic packet wakeup occurs only when the following conditions are met: ? the destination address of the r eceived magic packet is acceptable to the rtl8101e, e.g., a broadcast, multicast, or unicast packet addresse d to the current rtl8101e adapter. ? the received magic packet does not contain a crc error. ? the magic bit (config3#5) is set to 1, the pmen bit (config1#0) is set to 1, and the corresponding wake-up method (message, beacon, or lanwakeb) can be asserted in the current power state. ? the magic packet pattern matches, i.e. 6 * ffh + misc (can be none) + 16 * did (destination id) in any part of a valid ethernet packet. a wakeup frame event occurs only wh en the following conditions are met: ? the destination address of th e received wakeup frame is acceptable to the rtl8101e, e.g., a broadcast, multicast, or unicast addr ess to the current rtl8101e adapter. ? the received wakeup frame does not contain a crc error. ? the pmen bit (config1#0) is set to 1. ? the 16-bit crc a of the received wakeup frame matches the 16-bit crc of the sample wakeup frame pattern given by the local machine?s os. or , the rtl8101e is configured to allow direct packet wakeup, e.g., a broadcast, multic ast, or unicast network packet. note: 16-bit crc: the rtl8101e supports two norma l wakeup frames (covering 64 mask bytes from offset 0 to 63 of any incoming network packet) and three long wakeup frames (covering 128 mask bytes from offset 0 to 127 of any incoming network packet). the corresponding wake-up method (message, beacon, or lanwakeb) is asserted only when the following conditions are met: ? the pmen bit (bit0, config1) is set to 1. ? the pme_en bit (bit8, pmcsr) in pc i configuration space is set to 1. ? the rtl8101e may assert the corresponding wake -up method (message, beacon, or lanwakeb) in the current power state or in isolation state, de pending on the pme_support (b it15-11) setting of the pmc register in pci configuration space. ? a magic packet, linkup, or wakeup frame has been received. ? writing a 1 to the pme_status (bit15) of the pmcsr register in the pci configuration space clears this bit and causes the rtl8101e to stop asse rting the corresponding wake-up method (message, beacon, or lanwakeb) (if enabled). www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express 14 track id: jatr-1076-21 rev. 1.2 when the rtl8101e is in power down mode, e.g., d1-d3, the io and mem accesses to the rtl8101e are disabled. after a perstb assertion, the device?s pow er state is restored to d0 automatically if the original power state was d3 cold . there is almost no hardware delay at the device?s power state transition. when in acpi mode, the device does not support pme (power management enable ) from d0 (this is the realtek default setting of the pmc register auto -loaded from eeprom). the setting may be changed from the eeprom, if required. 6.6. vital product data (vpd) bit 31 of the vital product data (vpd) capability st ructure in the rtl8101e?s pci configuration space is used to issue vpd read/write commands and is also a flag used to indicate whether the transfer of data between the vpd data register and the 93c46/93c56 has completed or not. write vpd register: (write data to the 93c46/93c56) set the flag bit to 1 at the same time the vpd a ddress is written to writ e vpd data to eeprom. when the flag bit is reset to 0 by the rtl8101e, the vpd data (4 bytes per vpd access) has been transferred from the vpd data register to eeprom. read vpd register: (read data from the 93c46/93c56) reset the flag bit to 0 at the same time the vpd address is written to retrieve vpd data from eeprom. when the flag bit is set to 1 by the rtl8101e, the vpd data (4 bytes per vpd access) has been transferred from eeprom to the vpd data register. note1: refer to the pci 2.2 specifi cations for further information. note2: the vpd address must be a dword-aligned address as defined in th e pci 2.2 specifications. vpd data is always consecutive 4-byte dat a starting from the vpd address specified. note3: realtek reserves offset 40h to 7fh in eeprom, mainly for vpd data to be stored. note4: the vpd function of the rtl8101e is desi gned to be able to acce ss the full range of the 93c46/93c56 eeprom. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express 15 track id: jatr-1076-21 rev. 1.2 7. characteristics 7.1. absolute maximum ratings warning: absolute maximum ratings are limits beyond which permanent damage may be caused to the device, or device reliability will be affected. all voltages are specified reference to gnd unless otherwise specified. table 11. absolute maximum ratings symbol description minimum maximum unit vdd33, avdd33 supply voltage 3.3v -0.5 4.6 v avdd18, evdd18 supply voltage 1.8v -0.5 2.1 v vdd15 supply voltage 1.5v -0.5 2 v dcinput input voltage -0.5 corresponding supply voltage + 0.5 v dcoutput output voltage -0.5 corresponding supply voltage + 0.5 v storage temperature -55 +125 c * refer to the most updated schematic circuit for correct configuration. 7.2. recommended operating conditions table 12. recommended operating conditions description pins minimum typical maximum unit vdd33, avdd33 3.0 3.3 3.6 v avdd18, evdd18 1.62 1.8 1.98 v supply voltage vdd vdd15 1.35 1.5 1.65 v ambient temperature t a - 0 - 70 c maximum junction temperature - - - 125 c * refer to the most updated schematic circuit for correct configuration. 7.3. crystal requirements table 13. crystal requirements symbol description/condition minimum typical maximum unit f ref parallel resonant crystal reference frequency, fundamental mode, at-cut type. - 25 - mhz f ref stability parallel resonant crystal frequency stability, fundamental mode, at-cut type. t a =25 c. -50 - +50 ppm f ref tolerance parallel resonant crystal frequency tolerance, fundamental mode, at-cut type. t a =-20 c ~+70 c. -30 - +30 ppm f ref duty cycle reference clock input duty cycle. 40 - 60 % c l load capacitance. - - pf esr equivalent series resistance. - - 30 ? dl drive level. - - 0.5 mw www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express 16 track id: jatr-1076-21 rev. 1.2 7.4. transformer characteristics table 14. transformer characteristics parameter transmit end receive end turn ratio 1:1 ct 1:1 inductance (min.) 350h @ 8ma 350h @ 8ma note: the auto-crossover detection function requires a transformer with symmetrical tx/rx and choke after transformer placement, i.e. pulse engi neer h1251 (refer to the suggested rtl8101e schematic which is available for download at www.realtek.com.tw. 7.5. thermal characteristics table 15. thermal characteristics parameter minimum maximum units storage temperature -55 +125 c ambient operating temperature 0 70 c 7.6. dc characteristics table 16. dc characteristics symbol parameter conditions minimum typical maximum units vdd33, avdd33 3.3v supply voltage - 3.0 3.3 3.6 v avdd18, evdd18 1.8v supply voltage - 1.62 1.8 1.98 v vdd15 1.5v supply voltage - 1.35 1.5 1.65 v vo h minimum high level output voltage ioh = -8ma 0.9 * vdd33 - vdd33 v vo l maximum low level output voltage iol = 8ma - 0.1 * vdd33 v vih minimum high level input voltage - 0.5 * vdd33 - vdd33+0.5 v vil maximum low level input voltage - -0.5 - 0.3 * vdd33 v iin input current vin = vdd33 or gnd -1.0 - 1.0 a icc33 average operating supply current from 3.3v - - tbd - ma icc18 average operating supply current from 1.8v - - tbd - ma icc15 average operating supply current from 1.5v - - tbd - ma * refer to the most updated schematic circuit for correct configuration. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express 17 track id: jatr-1076-21 rev. 1.2 7.7. ac characteristics 7.7.1. serial eeprom interface timing 93c46(64*16)/93c56(128*16) eesk eecs eedi eedo 11 0 an a2 a0 a1 dn d1 d0 eesk (read) (write) (read) (write) 0 tcs eesk eecs eedi eedo 11 0 an a0 ... dn tcs ... busy ready high impedance high impedance twp eecs eedi eedo eedo (read) (program) status valid tsk tskh tskl tcss tdis tdih tdos tdoh tcsh tsv d0 figure 6. serial eeprom interface timing table 17. eeprom access timing parameters symbol parameter eeprom type min. max. unit tcs minimum cs low time 9346 1000 - ns twp write cycle time 9346 - 10 ms tsk sk clock cycle time 9346 4 - s tskh sk high time 9346 1000 - ns tskl sk low time 9346 1000 - ns tcss cs setup time 9346 200 - ns tcsh cs hold time 9346 0 - ns tdis di setup time 9346 400 - ns tdih di hold time 9346 400 - ns tdos do setup time 9346 2000 - ns tdoh do hold time 9346 - 2000 ns tsv cs to status valid 9346 - 1000 ns www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express 18 track id: jatr-1076-21 rev. 1.2 7.8. pci express bus parameters 7.8.1. differential transmitter parameters table 18. differential transmitter parameters symbol parameter min typical max units ui unit interval 2 399.88 400 400.12 ps v tx-diffp-p differential peak to peak output voltage 0.800 - 1.2 v v tx-de-ratio de-emphasized differential output vo ltage (ratio) -3.0 -3.5 -4.0 db t tx-eye minimum tx eye width 0.70 - - ui t tx-eye-median- to-max-jitter maximum time between the jitter median and maximum deviation from the median - - 0.15 ui t tx-rise , t tx-fall d+/d- tx output rise/fall time 0.125 - - ui v tx-cm-acp rms ac peak common mode output voltage - 20 mv v tx-cm-dcactive- idledelta absolute delta of dc common mode voltage during l0 and electrical idle 0 - 100 mv v tx-cm-dcline- delta absolute delta of dc common mode voltage between d+ and d- 0 - 25 mv v tx-idle-diffp electrical idle differential peak output voltage 0 - 20 mv v tx-rcv-detect the amount of voltage chan ge allowed during receiver detection - - 600 mv v tx-dc-cm the tx dc common mode voltage 0 - 3.6 v i tx-short tx short circuit current limit - 90 ma t tx-idle-min minimum time spent in electrical idle 50 - - ui t tx-idle- setto-idle maximum time to transition to a valid electrical idle after sending an electrical idle ordered set - - 20 ui t tx-idle-toto- diff-data maximum time to transition to valid tx specifications after leaving an electrical idle condition - - 20 ui rl tx-diff differential return loss 12 - - db rl tx-cm common mode return loss 6 - - db z tx-diff-dc dc differential tx impedance 80 100 120 ? z tx-dc transmitter dc impedance 40 - - ? l tx-skew lane-to-lane output skew - - 500+2 ui ps c tx ac coupling capacitor 75 - 200 nf t crosslink crosslink random timeout 0 - 1 ms note1: refer to pci express base specification, rev.1. 0a, for correct measurement environment setting of each parameter. note2: the data rate can be modulated with an ssc (spread spectrum clock) from +0 to -0.5% of the nominal data rate frequency, at a modulation rate in th e range not exceeding 30 khz ? 33 khz. the +/- 300 ppm requirement still holds, which requires the two communicating port s be modulated such that they never exceed a total of 600 ppm difference. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express 19 track id: jatr-1076-21 rev. 1.2 7.8.2. differential receiver parameters table 19. differential receiver parameters symbol parameter min. typical max. units ui unit interval 399.88 400 400.12 ps v rx-diffp-p differential input peak to peak voltage 0.175 - 1.200 v t rx-eye minimum receiver eye width 0.4 - - ui t rx-eye-median-to- max-jitter maximum time between the jitter median and maximum deviation from the median - - 0.3 ui v rx-cm-acp ac peak common mode input voltage - - 150 mv rl rx-diff differential return loss 15 - - db rl rx-cm common mode return loss 6 - - db z rx-diff-dc dc differential input impedance 80 100 120 ? z rx--dc dc input impedance 40 50 60 ? z rx-high-imp-dc powered down dc input impedance 200 k - - ? v rx-idle-det-diffp-p electrical idle detect threshold 65 - 175 mv t rx-idle-det- diffentertime unexpected electrical idle enter detect threshold integration time - - 10 ms l rx-skew total skew - - 20 ns note: refer to pci express base specification, rev.1.0a, for correct measurement environment setting of each parameter. 7.8.3. refclk parameters table 20. refclk parameters symbol parameter 100mhz input min max units t absmin absolute min. dif clk period 9.872 - ns t rise rise time 175 700 ps t fall fall time 175 700 ps h ? t rise rise time variation - 125 ps ? t fall fall time variation - 125 ps rise/fall matching - 20 % v high voltage high (typical 0.71v) 660 850 mv v low voltage low (typical 0.0v) -150 - mv v cross absolute absolute crossing point voltages 250 550 mv v cross relative relative crossing point voltages note 2 note 2 v total ? v cross total variation of v cross over all edges - 140 mv t ccjitter cycle to cycle jitter - 125 ps duty cycle 45 55 % v ovs maximum voltage (overshoot) - v high_avg + 0.3 v v uds minimum voltage (undershoot) - -0.3 v v rb ringback voltage 0.2 n/a v note1: refer to pci express base specification, rev.1. 0a, for correct measurement environment setting of each parameter. note2: vcross relative min = 0.5(vhigh_avg ? 0.710) + 0.25 0, vcross relative max = 0.5(vhigh_avg ? 0.710) + 0.550. the crossing point must meet the absolute and relative crossing point specifications simultaneously. note3: the nominal single-ended swing for each clock is 0 to 0.7v with a nominal frequency of 100mhz 300 ppm. note4: the reference clocks may support spread spectrum clocking. the minimum clock period cannot be violated. - www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express 20 track id: jatr-1076-21 rev. 1.2 figure 7. refclk single-ended measurement points for t rise and t fall figure 8. refclk single-ended measurement points for v ovs , v uds, and v rb figure 9. refclk differenti al measurement points for t period , duty cycle, and jitter www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express 21 track id: jatr-1076-21 rev. 1.2 figure 10. refclk v cross range 7.8.4. auxiliary signal timing parameters table 21. auxiliary signal timing parameters symbol parameter min max units t pvperl power stable to perstb inactive 100 - ms t perst-clk refclk stable before perstb inactive 100 - s t perst perstb active time 100 - s t fail power level invalid to pwrgd inactive - 500 ns t wkrf lanwakeb rise ? fall time - 100 ns 3.3 vaux 3.3/12v perstb refclk pci-e link power stable inactive active inactive wakeup event t t t perst t fail clock not stable pvperl perst-clk active clock stable clock stable power stable figure 11. auxiliary signal timing www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8101E-GR datasheet integrated fast ethernet controller for pci express 22 track id: jatr-1076-21 rev. 1.2 8. mechanical dimensions 9. ordering information table 22. ordering information part number package status RTL8101E-GR 64-pin qfn ?green? package production note: see page 3 for package id information. realtek semiconductor corp. headquarters no. 2, innovation road ii hsinchu science park, hsinchu 300, taiwan tel.: +886-3-578-0211. fax: +886-3-557-6047 www.realtek.com.tw note: rtl8101e?s exposed pad size is l/f 3 www.datasheet.co.kr datasheet pdf - http://www..net/

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